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8008H–AVR–04/11

ATtiny48/88

ized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is

enabled.

11.5.2

Using the Output Compare Unit

Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock

cycle, there are risks involved when changing TCNT0 when using the Output Compare Unit,

independently of whether the Timer/Counter is running or not. If the value written to TCNT0

equals the OCR0x value, the compare match will be missed, resulting in incorrect waveform

generation.

11.6

Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the CTC0 bit.

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 84.

11.6.1

Normal Mode

The simplest mode of operation is the Normal mode (CTC0 = 0). In this mode the counting direc-

tion is always up (incrementing), and no counter clear is performed. The counter simply overruns

when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00).

In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock

cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except

that it is only set, not cleared. However, combined with the timer overflow interrupt that automat-

ically clears the TOV0 Flag, the timer resolution can be increased by software. There are no

special cases to consider in the Normal mode, a new counter value can be written anytime.

The Output Compare unit can be used to generate interrupts at some given time.

11.6.2

Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (CTC0 = 1), the OCR0A Register is used to manipu-

late the counter resolution. In CTC mode the counter is cleared to zero when the counter value

(TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence also its

resolution. This mode allows greater control of the compare match output frequency. It also sim-

plifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 11-4. The counter value (TCNT0)

increases until a compare match occurs between TCNT0 and OCR0A, and then counter

(TCNT0) is cleared.

Figure 11-4. CTC Mode, Timing Diagram

TCNTn

OCnx Interrupt Flag Set

Period

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